1. Field of the Invention
The present invention relates to a semiconductor device formed on an SOI (semiconductor on insulator) substrate and particularly to a semiconductor device having a trench provided on a direct bonded SOI substrate.
For high speed operation of a semiconductor device, particularly, of a MOS transistor, it is one of the effective methods to make smaller a parasitic capacitance thereof, for example, a capacitance between a diffused layer or metal wiring and a silicon substrate. As a method for this purpose, a substrate having the so-called SOI structure (hereinafter called simply SOI substrate) is used. That is, when a substrate on which a device is formed (this is called a device substrate) is formed through an insulator layer provided on a substrate for supporting the entire part (it is called a base substrate), a more perfect element isolation structure can be realized and a parasitic capacitance can be lowered. For the SOI substrate, a direct bonded SOI substrate, which is obtained by bonding directly a pair of silicon substrates, is attracting, in these years, the most distinctive attention because of its superiority in the fabrication cost and matching with the conventional fabrication process.
Moreover, the requirement for further miniaturization of the device results in the reduction in size of individual transistors to be formed in an LSI (Large Scale Integrated Circuit). However, the size of regions between transistors must also be reduced. For example, in the case of a structure of MOS-LSI wherein a thick oxide film is provided as the device isolation region at the surface between transistors, when the size of region between transistors becomes smaller, a punch-through between transistors becomes a problem. Such punch-through becomes difficult to be formed when the surface concentration of a silicon layer between transistors is made high but when the surface concentration of the silicon layer becomes higher, a junction capacitance becomes large, resulting in the interference with high speed operation of device. As a method of solving such problem, a device providing the trench isolation structure has been proposed.
As described above, a device providing the trench isolation structure on the direct bonded SOI substrate has been considered which is very effective for realizing high speed operation.
2. Description of the Related Art
Initially, a trench isolation structure formed on the conventional direct bonded SOI substrate will be explained.
FIG. 1 is a sectional view of a trench isolation structure where a base substrate 31 which is a silicon substrate and a device substrate 33 which is the other silicon substrate are bonded and a device having trench is formed therein. A silicon oxide insulating film 32a is formed to the one surface of the base substrate by the thermal oxidization and a silicon oxide insulating film 32b is formed also to the one surface of the device substrate 33. Then the insulating film 32a is brought into contact with the insulating film 32b. Thereafter, the insulating film 32a and insulating film 32b are bonded at the interface of the insulating film 32a and insulating film 32b, namely at the bonding surface 34 by conducting the annealing for two hours at the temperature of about 1200.degree. C.
The trench 35 is formed on the device substrate 33 by silicon etching and the bottom of the trench 35 usually lies on the interface between the insulating film 32b and device substrate 33. In the trench 35, an insulating film 36 consisting of Si nitride, etc. and a conductive film 37 is provided in order to suppress charge storing. As explained above, the trench isolation structure is formed.
Combination of such a trench isolation structure and SOI substrate structure mutually separates device such as MOS transistor.
Such a trench isolation structure formed on the direct bonded SOI substrate is disclosed, for example, in the Japanese Laid-open Patent Application No. HEI-106466, "A Method of Fabricating Semiconductor Device" filed by Hiroshi Gotoh, on Oct. 19, 1987 (Application).
However, in such a structure, since a thermal expansion coefficient of polysilicon (poly-Si) forming a conductive film 37 buried in the trench 35 is larger than that of single crystal Si forming the device substrate 33, when temperature rises in the device fabrication process, a stress as indicated by the arrow mark Y1 in FIG. 2 is generated in the side of the device substrate 33. As a result, crystalline defect is easily generated in the device substrate 33 and thereby a leak current at the p-n junction increases.
On the other hand, in such structure, under the operating condition, a voltage difference is generated between the device substrate 33 on which devices are formed and the conductive film 37 usually to be used under the condition as being earthed to the ground potential. In the case of a device shown in FIG. 2 a following problem is generated. That is, the surfaces of the device substrate 33 and conductive film 37 are set in the equal potential and the field is equalized in such an area where the distance between the device substrate 33 and conductive film 37 is equal but field concentration indicated by XI is occurred at the corner where distance between the device substrate 33 and conductive film 37 changes and thereby a dielectric breakdown voltage is easily deteriorated and device reliability is also lowered.
In addition, when the trench 35 is formed crossing the bonding surface 34 in the device fabrication process explained above, a problem rises. Namely, the bonded insulating film 32a and insulating film 32b are easily separated at the bonding surface 34 during the cleaning of the trench surface with the fluoric acid solution for cleaning the trench.
Because of such background problems, it has long and ardently been desired to develop a highly reliable SOI device and a method of manufacturing the same which does not generate separation between bonded layers and which provides the trench isolation structure.